![verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/and”---AND gate](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/and”---AND gate)
1、题目2、分析题目提供与门模块需要写对应的testbench模块3、代码module top_module(); reg [1:0]in; wire out; initial begin in2b00; #10 in2b01; #10 in2b10; #10 in2b11; end andgate andgate_inst(.in(in),.out(out)); endmodule4、结果 verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/and”---AND gate
1、题目2、分析题目提供与门模块需要写对应的testbench模块3、代码module top_module(); reg [1:0]in; wire out; initial begin in2b00; #10 in2b01; #10 in2b10; #10 in2b11; end andgate andgate_inst(.in(in),.out(out)); endmodule4、结果 RELATED READING
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![verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/tb1”---Testbench1](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/tb1”---Testbench1)
