一、引言在使用 Vivado 2020.2 进行 FPGA 开发的过程中笔者整理并记录了多个实际遇到的问题现象及对应的解决方案。本文将这些经验汇总成文供大家参考。部分问题尚未找到根本原因或解决方案已在文中标注欢迎大家在评论区一起讨论。二、IP 相关报错1. [Designutils 20-1280] Could not find module XDC问题现象在 Vivado 2020.2 中当工程中存在未使用的 IP 时使用 generate 选择使用哪个 IP 时会出现如下报错[Designutils 20-1280] Could not find module serdes_rx_dis_std_fifo_64bx16. The XDC file d:/1_Vivado_2020/516_N35_k7_160_z7020_32ch/z7020_32ch_all_vdma_lcd_v2020.1/02_ipcore/pl_serdes/serdes_rx_dis_std_fifo_64bx16/serdes_rx_dis_std_fifo_64bx16.xdc will not be read for any cell of this module.原因分析Vivado 2020.2 版本中如果 define 宏定义没有引用某个模块并且没有 refresh 完全就会触发该错误。这属于 Vivado 的一个 bug通常需要 refresh 两次才能更新成功。解决方案对工程进行两次 refresh 操作确保所有 IP 的 XDC 文件都被正确加载。2. IP 导入升级失败问题现象在升级或导入 IP 时出现如下报错ERROR: [Vivado 12-3445] A collection of objects is currently not supported at this time. Please provide only one sub-design. ERROR: [Common 17-69] Command failed: ERROR: [Vivado 12-3445] A collection of objects is currently not supported at this time. Please provide only one sub-design.解决方案在 report ip status 中对单个 IP 进行升级排除无法升级的 IP然后 remove ip再重新导入多次尝试。注意事项该问题的根本原因是在 reset_project 后不要移动 IP 的目录。即使移动后打开 Vivado 重新导入再移到新的 Vivado 也会出问题。必须在完整编译完、reset project 后完整地导入新 Vivado 进行升级不要移动任何文件。三、时钟相关报错1. [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair问题现象在实现阶段出现如下报错[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets DSP2BF_SYS_CLK_IBUF] 解决方案根据报错提示在 XDC 文件中添加对应的 CLOCK_DEDICATED_ROUTE 约束将错误降级为警告。例如set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets DSP2BF_SYS_CLK_IBUF]但需要注意使用该覆盖方法需要谨慎评估对时序的影响。2. [Place 30-99] Placer failed with error: IO Clock Placer failed问题现象在布局阶段出现如下报错[Place 30-99] Placer failed with error: IO Clock Placer failed [Common 17-69] Command failed: Placer could not place all instances原因分析经过排查发现是某个信号加了(*mark_debug true*)导致 Debug 出错。把 XDC 中的 Debug 全部删掉可以编译通过但原本 Debug 正常的信号在加上(*mark_debug true*)后 Debug 就不正常这应该是产生了约束冲突。解决方案排查发现以下三个信号任意一个加上 debug 都会导致报错需要检查并调整这些信号的 Debug 约束设置。3. OSERDES invalid clock topology问题现象出现如下 DRC 报错[DRC REQP-1975] OSERDES invalid clock topology: Unsupported clocking topology used for OSERDESE2 disp_serdes_tx_inst/serdes_tx/inst/pins[0].oserdese2_master. This can result in corrupted data. The disp_serdes_tx_inst/serdes_tx/inst/pins[0].oserdese2_master/CLK / disp_serdes_tx_inst/serdes_tx/inst/pins[0].oserdese2_master/CLKDIV pins should be driven by the same source through the same buffer type or by a BUFIO / BUFR combination in order to have a proper phase relationship.解决方案Vivado 2020.2 需要 BUFG 才能通过该检查而 Vivado 2018 则不需要。需要根据版本调整时钟缓冲器的使用。4. [DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk问题现象出现如下报错[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 640.000 MHz (CLKIN1_PERIOD, net clk_out3) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y0 falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1866.000 MHz).原因分析时钟设置本身是对的但是约束不匹配造成。改了时钟结构记得约束也要同步修改。解决方案检查并同步更新时钟约束确保约束与时钟结构匹配。5. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk问题现象出现如下报错[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 503.750 MHz (CLKIN1_PERIOD, net clk_out1) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y1 falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz).原因分析同样是时钟设置正确但约束不匹配造成。解决方案检查并同步更新时钟约束确保约束与时钟结构匹配。6. [Place 30-458] The loads of regional clock BUF (BUFR) instance are locked in multiple clock regions问题现象在实现阶段出现如下报错[Place 30-458] The loads of regional clock BUF (BUFR) instance bf_serdes_rx/bf_serdes_rx_bitslip/bf_serdes_ddr_exclk_rx_inst/inst/clkout_buf_inst are locked in multiple clock regions. A BUFR can drive loads in only one clock region.原因分析BUFR 输出的时钟不能同时驱动 MMCM 和其他模块工作需要分出时钟再接到其他地方。解决方案将 BUFR 输出的时钟进行分路分别接到不同的模块。7. Clock Rule-CLOCK_DEDICATED_ROUTE问题现象出现如下报错[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. Clock Rule: rule_mmcm_bufg Status: FAIL Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device ERROR: The above is also an illegal clock rule Workaround: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets inst_clk0/inst/clk_out1_bf_clk_wiz_0] 解决方案根据报错提示在 XDC 文件中添加对应的 CLOCK_DEDICATED_ROUTE 约束例如set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets inst_clk0/inst/clk_out1_bf_clk_wiz_0]8. [Place 30-150] Sub-optimal placement for an MMCM-BUFG component pair问题现象出现如下报错[Place 30-150] Sub-optimal placement for an MMCM-BUFG component pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.解决方案根据报错提示在 XDC 文件中添加对应的 CLOCK_DEDICATED_ROUTE 约束。9. DDR 参考时钟问题-IDELAYCTRL问题现象出现如下报错[Timing 38-472] The REFCLK pin of IDELAYCTRL bram_pcie_i/mig_7series_0/u_bram_pcie_bd_mig_7series_0_1_mig/u_iodelay_ctrl/u_idelayctrl_200 is not reached by any clock but IDELAYE2 ... has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property value.原因分析因为是 Block design输入的时钟 PIN 要给约束否则就会报以上错误。解决方案添加时钟约束例如create_clock -period 25.000 -name sys_clk [get_ports sys_clk]四、其他问题1. Multiple Driver Nets-GND/G, and VCC/P问题现象出现如下报错[DRC MDRV-1] Multiple Driver Nets: Net const1 has multiple drivers: dsp_proc_top/GND/G, and VCC/P.原因分析IO 端口作为输出但是连接的端口wire被 assign 赋值了或者两个输出端口被连到一起就会报这个错。解决方案删除导致冲突的 assign 赋值语句避免输出端口被误输入信号或连接了其他模块的输出端口。2. DCP does not exist问题现象出现如下报错[Runs 36-527] DCP does not exist: d:/1_Vivado_2020/550_N3_A7_PC_32CH_201/pcie_test/08_example/fpga/project/.Xil/Vivado-14224-DESKTOP-TIBVN2H/coregen/bram_pcie_bd_mig_7series_0_1/bram_pcie_bd_mig_7series_0_1.dcp解决方案reset ip重新综合即可。3. .runs 目录被异常占用编译警告解决方案关掉 Vivado删掉 .runs 目录重新打开 Vivado 重新编译。如果不行就 reset_project 再删 .runs 再重开 Vivado 编译。五、总结以上是笔者在使用 Vivado 2020.2 过程中遇到的部分问题及解决方案。希望这些经验能对大家有所帮助。如果大家有更好的解决方案或遇到类似问题欢迎在评论区留言讨论。